View IA80C152JD_1252483.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Page 1 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
FEATURES
* Form, Fit, and Function Compatible with the Intel(R) 80C152 * Packaging options available - 48 Pin Plastic or Ceramic DIP - 68 Pin Plastic or Ceramic LCC * 8051 Core with: - Direct Memory Access(DMA) - Global Serial Channel (GSC) - MCS(R) - 51 Compatible UART - Two Timers/Counters - Maskable Interrupts * Memory - 256 Bytes Internal RAM - 64K Bytes Program Memory - 64K Bytes Data Memory * 5 or 7 I/O Ports * Up to 16.5 MHz Clock Frequency * Two-Channel DMA With Multiple Transfer Modes * GSC Provides Support for Multiple Protocols - CSMA/CD - SDLC/HDLC - User Definable * Separate Transmit & Receive FIFOs * Special Protocol Features - Up to 2.0625 Mbps Serial Operation - CSMA and SDLC Frame Formats with CRC Checking - Manchester, NRZ, & NRZI Data Encoding - Collision Detection & Resolution in CSMA Mode - Selectable Full/Half Duplex
(GRXD) P1.0 (GTXD) P1.1 (DENn) P1.2 (TXCn) P1.3 (RXCn) P1.4 (HLDn) P1.5 (HLDAn) P1.6 P1.7 RESETn (RXD) P3.0 (TXD) P3.1 (INT0n) P3.2 (INT1n) P3.3 (T0) P3.4 (T1) P3.5 (WRn) P3.6 (RDn) P3.7 (A / D0) P0.0 (A / D1) P0.1 (A / D2) P0.2 (A / D3) P0.3 XTAL2 XTAL1 Vss
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24)
IA80152
(48) (47)
VDD P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 EA ALE PSENn P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) P0.7 (A / D7) P0.6 (A / D6) P0.5 (A / D5) P0.4 (A / D4)
48 Pin DIP (46) JA/JC
(45) (44) (43) (42) (41) (40) (39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25)
Figure 1 - 48 Pin DIP Pinout
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 2 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
P1.0 (GRXD) P1.1 (GTXD) P1.2 (DENn) P1.4 (RXCn) P1.5 (HLDn) P1.3 (TXCn)
VDD
P4.0
P4.1
P4.2
P4.3 (62)
(9)
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(68)
(67)
(66)
(65)
(64)
(63)
(HLDAn) P1.6 P1.7 N.C. RESETn (RXD) P3.0 (TXD) P3.1 (INT0n) P3.2 N.C. (INT1n) P3.3 (T0) P3.4 N.C. N.C. N.C. (T1) P3.5 (WRn) P3.6 (RDn) P3.7 N.C.
(10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43)
(61) (60) (59)
P4.4
N.C.
N.C.
N.C.
N.C.
Vss
P4.5 P4.6 P4.7 N.C. EA ALE PSENn N.C. N.C. N.C. N.C. N.C. P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11)
IA82510 68 Pin LCC JA/JC
(58) (57) (56) (55) (54) (53) (52) (51) (50) (49) (48) (47) (46) (45) (44)
Vss
N.C.
N.C.
N.C.
(A8) P2.0
(A / D0) P0.0
(A / D1) P0.1
(A / D2) P0.2
(A / D3) P0.3
(A / D4) P0.4
(A / D5) P0.5
(A / D6) P0.6
(A / D7) P0.7
(A9) P2.1
P4.3 (62)
XTAL2
XTAL1
Figure 2 - 68 Lead LCC Pinout - JA/JC Versions
P1.0 (GRXD) P1.1 (GTXD) P1.2 (DENn) P1.4 (RXCn) P1.5 (HLDn) P1.3 (TXCn)
VDD
P6.6
P6.5
P6.0
P6.1
P4.0
P4.1
P4.2
(68)
(67)
(66)
(65)
(64)
(63)
(61) (60) (59)
(9)
(8)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
P4.4
Vss
(A10) P2.2
(HLDAn) P1.6 P1.7 EBEN RESETn (RXD) P3.0 (TXD) P3.1 (INT0n) P3.2 P5.0 (INT1n) P3.3 (T0) P3.4 P5.1 P5.2 P5.3 (T1) P3.5 (WRn) P3.6 (RDn) P3.7 N.C.
(10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43)
P4.5 P4.6 P4.7 P6.3 EA ALE PSENn EPSENn P6.2 P6.7 P6.4 P5.7 P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11)
IA82510 68 Pin LCC JB/JD
(58) (57) (56) (55) (54) (53) (52) (51) (50) (49) (48) (47) (46) (45) (44)
P5.4
P5.5
P5.6
Vss
(A8) P2.0
(A / D0) P0.0
(A / D1) P0.1
(A / D2) P0.2
(A / D3) P0.3
(A / D4) P0.4
(A / D5) P0.5
(A / D6) P0.6
(A / D7) P0.7
(A9) P2.1
XTAL2
XTAL1
Figure 3 - 68 Lead LCC Pinout - JB/JD Versions
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
(A10) P2.2
Page 3 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
The IA80C152 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA80C152 including functional and I/O descriptions, electrical characteristics, and applicable timing.
INTEL is a registered trademark of Intel Corporation
DESCRIPTION
The IA80C152 is a Universal Communications Controller (UCC) that is pin-for-pin compatible with the IntelTM 80C152. This version of the UCC is a ROMless version. The ROM version is identified as the 83C152 and can be easily derived from the 80C152 using a customer furnished ROM program. The IA80C152 can be programmed with the same software development tools and can transmit and receive using the same communication protocols as the IntelTM 80C152 making the IA80C152 a drop-in replacement. Table 1 below cross-references IA80C152 versions with protocol, package, and I/O Port capability. Pinout diagrams are provided in figures 1, 2, and 3. Table 1 - IC Version Differences CSMA/CD, SDLC/HDLC, 5 I/O 7 I/O User-Defined Ports Ports 48 Pin DIP
innovASIC Part Number IA80C152JA IA80C152JB IA80C152JC IA80C152JD
68 Lead LCC
The only difference between The innovASIC 80C152 and the IntelTM 80C152 is that all protocols are available in all IC versions. Originally, the IntelTM 80C152 JC and JD versions were limited to SDLC/HDLC only. Also, innovASIC will support a ROM version (83152) in any of the JA, JB, JC, or JD versions. The IA80C152 is partitioned into three major functional units identified as the C8051, the Direct Memory Access (DMA) Controller, and the Global Serial Channel (GSC). The C8051 is implemented using a CAST, Inc. Intellectual Property (IP) core. This core is instruction set compatible with the 80C51BH, and contains compatible peripherals including a UART interface and timers. The special function registers (SFRs) and interrupts are modified from the original 8051BH to accommodate the additional DMA controller and GSC peripherals. The DMA Controller is a 2 channel, 8-bit device that is 16-bit addressable. Either channel can access any combination of reads and writes to external memory, internal memory, or the SFR's. Various modes allow the DMA to access the UART, GSC, SFRs, and internal and external memory as well as provide for external control. Since there is only 1 data/program memory bus, only one DMA channel or the microcontroller can have control at any give time. Arbitration within the device makes this control transparent to the programmer.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 4 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
The GSC is a serial interface that can be programmed to support CSMA/CD, SDLC, user definable protocols, and limited HDLC. Protocol specific features are supported in hardware such as address recognition, collision resolution, CRC generation and errors, automatic re-transmission, and hardware acknowledge. The CSMA/CD protocol meets the requirements of ISO/IEC 8802-3 and ANSI/IEEE Std 802.3 to the extent implemented in the original IC. The SDLC protocol meets the requirements of IBM GA27-3093-04 to the extent implemented in the original IC.
Functional Block Diagram
Figure 4 shows the major functional blocks of the IA80C152. Each version of the IA80C152 function identically to each other with the exception of the 2 additional I/O ports (Port 5 and Port 6) in the JB and JD versions.
I/O for Memory, GSC, DMA, UART, Interrupts, Timers
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Memory Control XTAL Reset Clock Gen. & Timing 256x8 RAM C8051 CPU Control
Address/Data
UART
Interrupts
Timers
DMA
GSC
= JB and JD Versions Only
Figure 4 - Functional Block Diagram
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 5 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
I/O Signal Description
Table 2 below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided above. (!) Denotes active Low.
Table 2 - I/O Signal Descriptions Signal Name !EA !EPSEN !PSEN !RESET Description External Access enable. Since there is no internal ROM in the 80C152, this signal has no function in the JA and JC versions. For the JB and JD versions, controls program memory fetch locations. E-bus Program Store ENable. When EBEN is 1, this signal is the read strobe for external program memory. Program Store ENable. When EBEN is 0, this signal is the read strobe for external program memory. Reset. When this signal is low for 3 machine cycles, the device is put into reset. The GSC may continue transmitting after reset is applied. An internal pull-up allow the use of an external capacitor to generate a power-on reset. Address Latch Enable. Latches the low-byte of external memory. E-Bus ENable. In conjunction with EA, EBEN designates program memory fetches from either Port 0,2 or Port 5,6. Port 0 - open drain 8-bit bi-directional port that bit addressable and can drive up to 8 LS TTL inputs. The port signals can be used as high impedance inputs. This port also provides the low-byte of the multiplexed address and data bus depending on the state of !EBEN.
ALE EBEN P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 - GRXD, GSC Receive P1.1 - GTXD, GSC Transmit P1.2 - !DEN, Driver Enable P1.3 - !TXC, External Transmit Clock P1.4 - !RXC, External Receive Clock P1.5 - !HLD, DMA Hold P1.6 - !HLDA, DMA Hold Acknowledge P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 - RXD, UART Receive P3.1 - TXD, UART Transmit P3.2 - !INT0, External Interrupt 0 P3.3 - !INT1, External Interrupt 1 P3.4 - T0, Timer 0 External Input P3.5 - T1, Timer 1 External Input P3.6 - !WR, External Data Memory Write Strobe P3.7 - !RD, External Data Memory Read Strobe P4.0 P4.1 P4.2
Port 1 - 8-bit bi-directional port that is bit addressable. To use a port signal as an input, write a 1 to the port location. Internal pull-ups pull the input high and source current when the input is driven low. To use a port signal as an output, a 1 or 0 written to the port location is presented at the output. Port signals in this port also serve as I/O for 80C152 functions. These I/O signals are defined next to the port name. Port 2 - 8-bit bi-directional port that is bit addressable. To use a port signal as an input, write a 1 to the port location. Internal pull-ups pull the input high and source current when the input is driven low. To use a port signal as an output, a 1 or 0 written to the port location is presented at the output. This port also provides the high-byte of the multiplexed address and data bus depending on the state of !EBEN. Port 3 - 8-bit bi-directional port that is bit addressable. To use a port signal as an input, write a 1 to the port location. Internal pull-ups pull the input high and source current when the input is driven low. To use a port signal as an output, a 1 or 0 written to the port location is presented at the output. Port signals in this port also serve as I/O for 80C152 functions. These I/O signals are defined next to the port name. Port 4 - 8-bit bi-directional port that is bit addressable. To use a port signal as an input, write a 1 to the port location. Internal pull-ups pull the input high and source current when the input is driven low. To
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 6 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Table 2 - I/O Signal Descriptions Signal Name P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 VCC VSS XTAL1 XTAL2 Description use a port signal as an output, a 1 or 0 written to the port location is presented at the output.
Port 5 - 8-bit bi-directional port that is NOT bit addressable. To use the port as an input, write a 1 to the port location. Internal pull-ups pull the input high and source current when the input is driven low. To use the port as an output, 1s or 0s written to the port are presented at the output. This port also provides the low-byte of the multiplexed address and data bus depending on the state of !EBEN. Port 6 - 8-bit bi-directional port that is NOT bit addressable. To use the port as an input, write a 1 to the port location. Internal pull-ups pull the input high and source current when the input is driven low. To use the port as an output, 1s or 0s written to the port are presented at the output. This port also provides the high-byte of the multiplexed address and data bus depending on the state of !EBEN. Supply Voltage Device Ground Input to the internal clock generator Output from the internal oscillator amplifier
Memory Space
Memory space is divided up into program and data memory. Program memory is all external to the IA80C152. Data memory is divided up into external and internal data memory. There can be up to 64K bytes of external program and data memory. Internal data memory is 256 bytes that is mapped between RAM, SFRs, and Register Banks. Figure 5 diagrams the organization of the IA80C152 memory space. See the C8051 section for further details. Program memory is accessed using control signals and ports. On the JA and JC versions of the IA80C152 this access is performed through ports P0 and P2. Further, since there is no internal ROM, the entire program memory space is accessed via ports P0 and P2. On the JB and JD version of the IA80C152, program memory access can be through either ports P0 and P2, or ports P5 and P6. Which set of ports program memory fetches are made is controlled by the input signals !EA and !EBEN. Table 3 summarizes the IA80C152 versions and the relationship to program memory fetches.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 7 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
FFFFH
C000H
8000H FFH Upper 128 Bytes 4000H 80H 7FH Lower 128 Bytes 0000H External RAM 00H Internal RAM SFR Space
Figure 5 - Memory Space
Version JA, JC JB, JD
Table 3 - Summary of Program Memory Fetches Fetch Control Fetch Signal Fetch Ports PSEN EPSEN Memory Space EBEN EA N/A 0 or 1 P0, P2 Active 0h - FFFFh 0 0 P0, P2 Active 0h - FFFFh 1 0 P5, P6 Active 0h - FFFFh 1 1 P5, P6 Active 0h - 1FFFh P0, P2 Active 2000h - FFFFh
Summary of the 80C152 Registers and Interrupts
The 80C152 combines the register set of the 8051BH and additional SFRs for the DMA and GSC functions. Likewise, the 80C152 combines the interrupts of the 8051BH and the interrupts required by the DMA and GSC. Table 4 contains a summary of the 80C152 registers, and table 5 contains a summary of the 80C152 interrupts.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 8 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Item 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. Register Name A ADR0 ADR1 ADR2 ADR3 AMSK0 AMSK1 B BAUD BCRL0 BCRH0 BCRL1 BCRH1 BKOFF DARL0 DARH0 DARL1 DARH1 DCON0 DCON1 DPH DPL GMOD IE IEN1 IFS IP IPN1 MYSLOT P0 P1 P2 P3 P4 P5 P6 PCON PRBS PSW RFIFO RSTAT SARL0 SARH0 SARL1 SARH1 SBUF SCON SLOTTM SP TCDCNT TCON Register Address 0E0h 095h 0A5h 0B5h 0C5h 0D5h 0E5h 0F0h 094h 0E2h 0E3h 0F2h 0F3h 0C4h 0C2h 0C3h 0D2h 0D3h 092h 093h 083h 082h 084h 0A8h 0C8h 0A4h 0B8h 0F8h 0F5h 080h 090h 0A0h 0B0h 0C0h 091h 0A1h 087h 0E4h 0D0h 0F4h 0E8h 0A2h 0A3h 0B2h 0B3h 099h 098h 0B4h 081h 0D4h 088h Table 4 - SFR Summary Functional Block Description C8051 Accumulator GSC Address Match 0 GSC Address Match 1 GSC Address Match 2 GSC Address Match 3 GSC Address Mask 0 GSC Address Mask 1 C8051 B Register GSC Baud Rate DMA Byte Count Register (Low) 0 DMA Byte Count Register (High) 0 DMA Byte Count Register (Low) 1 DMA Byte Count Register (High) 1 GSC Backoff Timer DMA Destination Address Register (Low) 0 DMA Destination Address Register (High) 0 DMA Destination Address Register (Low) 1 DMA Destination Address Register (High) 1 DMA DMA Control 0 DMA DMA Control 1 C8051 Data Pointer High C8051 Data Pointer Low GSC GSC Mode C8051 Interrupt Enable DMA, GSC Interrupt Enable 1 GSC Interframe Space C8051 Interrupt Priority DMA, GSC Interrupt Priority 1 GSC GSC Slot Address C8051 Port 0 C8051 Port 1 C8051 Port 2 C8051 Port 3 C8051 Port 4 C8051 Port 5 C8051 Port 6 C8051 Power Control GSC Pseudo-Random Sequence C8051 Program Status Word GSC Receive FIFO GSC Receive Status DMA Source Address Register (Low) 0 DMA Source Address Register (High) 0 DMA Source Address Register (Low) 1 DMA Source Address Register (High) 1 C8051 Serial Channel Buffer (UART) C8051 Serial Channel Control (UART) GSC GSC Slot Time C8051 Stack Pointer GSC Transmit Collision Counter C8051 Timer Control
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Initial Value 00h 00h 00h 00h 00h 00h 00h 00h 00h X X X X X X X X X 00h 00h 00h 00h X0000000b 0XX00000b XX000000b 00h XXX00000b XX000000b 00h 0FFh 0FFh 0FFh 0FFh 0FFh 0FFh 0FFh 0XXX0000b 00h 00h X 00h X X X X X 00h 00h 07h X 00h
Page 9 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Item 52. 53. 54. 55. 56. 57. 58. Register Name TFIFO TH0 TH1 TL0 TL1 TMOD TSTAT Register Address 085h 08Ch 08Dh 08Ah 08Bh 089h 0D8h Table 4 - SFR Summary Functional Block Description GSC Transmit FIFO C8051 Timer (High) 0 C8051 Timer (High) 1 C8051 Timer (Low) 0 C8051 Timer (Low) 1 C8051 Timer Mode GSC Transmit Status Initial Value X 00h 00h 00h 00h 00h XX000100b
Interrupt Priority 1 2 3 4 5 6 7 8 9 10 11
Table 5 - Interrupt Summary Priority Enable Interrupt Symbol Symbol Priority Name Name Name Address Enable All Interrupts EA External Interrupt 0 PX0 EX0 0B8h GSC Receive Valid PGSRV EGSRV 0F8h Timer 0 Overflow PT0 ET0 0B9h GSC Receive Error PGSRE EGSRE 0F9h DMA Channel 0 Done PDMA0 EDMA0 0FAh External Interrupt 1 PX1 EX1 0BAh GSC Transmit Valid PGSTV EGSTV 0FBh DMA Channel 1 Done PDMA1 EDMA1 0FCh Timer 1 Overflow PT1 ET1 0BBh GSC Transmit Error PGSRE EGSRE 0FDh UART Transmit/Receive PS ES 0BCh
Enable Address 0AFh 0A8h 0C8h 0A9h 0C9h 0CAh 0AAh 0CBh 0CCh 0ABh 0CDh 0ACh
Vector Address 03h 2Bh 0Bh 33h 3Bh 13h 43h 53h 1Bh 4Bh 23h
Power Conservation Modes
There are 2 power conservation modes identified as Idle Mode and Power Down Mode. The IA80C152 pins will have values according to the Table 6 below. Idle Mode is entered through software control of the PCON register. Idle halts processor execution and the DMA. The GSC continue to operate to the extent that it can without the processor or DMA servicing its requests. Idle mode is exited upon receipt of any enabled interrupt or invoking a hardware reset. Power Down Mode is entered through software control of the PCON register. Power Down disables the oscillator causing all functions to stop. RAM data is maintained since power is not removed from the device. The only way to exit power down mode is to invoke a hardware reset.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 10 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Mode Idle Program Fetch P0, P2 P5, P6* Power Down P0, P2 P5, P6* ALE 1 1 0 0 Table 6 - Power Conservation Modes Port Port Port PSEN EPSEN* 0 1 2 1 1 Float Data Addr. 1 0 1 1 1 0 Data Float Data Data Data Data Data Data Data Port 3 Data Data Data Data Port 4 Data Data Data Data Port 5* 0FFh 0FFh 0FFh 0FFh Port 6* 0FFh Addr. 0FFh 0FFh
*JB and JD Versions Only
Oscillator Pins
There are 2 methods for providing a clock to the 80C152. One method is to provide a crystal oscillator and the other method is to provide an external clock source. When providing a crystal oscillator, the XTAL1 pin is the input and XTAL2 is the output. The min and max crystal frequencies are 3.5 MHz and 16.5 MHz, respectively. When providing an external clock source, XTAL1 is the input and XTAL has no connection. Duty cycle does not matter to the device, however, the external clock source requires a minimum pulse width of 20 ns.
Summary of the 8051 Instruction Set
Table 7 provides a summary of the instruction set organized by hexadecimal opcode. Please refer to the original IntelTM Data Book for individual instruction set details.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 11 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Opcode 00 H 01 H 02 H 03 H 04 H 05 H 06 H 07 H 08 H 09 H 0A H 0B H 0C H 0D H 0E H 0F H 10 H 11 H 12 H 13 H 14 H 15 H 16 H 17 H 18 H 19 H 1A H 1B H 1C H 1D H 1E H 1F H 20 H 21 H 22 H 23 H 24 H 25 H 26 H 27 H 28 H 29 H 2A H 2B H 2C H 2D H 2E H 2F H 90 H 91 H 92 H Mnemonic NOP AJMP addr11 LJMP addr16 RR A INC A INC direct INC @R0 INC @R1 INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 JBC bit,rel ACALL addr11 LCALL addr16 RRC A DEC A DEC direct DEC @R0 DEC @R1 DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 JB bit.rel AJMP addr11 RET RL A ADD A,#data ADD A,direct ADD A,@R0 ADD A,@R1 ADD A,R0 ADD A,R1 ADD A,R2 ADD A,R3 ADD A,R4 ADD A,R5 ADD A,R6 ADD A,R7 MOV DPTR,#data16 ACALL addr11 MOV bit,C Table 7 - Instruction Set Summary Opcode Mnemonic 30 H JNB bit.rel 31 H ACALL addr11 32 H RETI 33 H RLC A 34 H ADDC A,#data 35 H ADDC A,direct 36 H ADDC A,@R0 37 H ADDC A,@R1 38 H ADDC A,R0 39 H ADDC A,R1 3A H ADDC A,R2 3B H ADDC A,R3 3C H ADDC A,R4 3D H ADDC A,R5 3E H ADDC A,R6 3F H ADDC A,R7 40 H JC rel 41 H AJMP addr11 42 H ORL direct,A 43 H ORL direct,#data 44 H ORL A,#data 45 H ORL A,direct 46 H ORL A,@R0 47 H ORL A,@R1 48 H ORL A,R0 49 H ORL A,R1 4A H ORL A,R2 4B H ORL A,R3 4C H ORL A,R4 4D H ORL A,R5 4E H ORL A,R6 4F H ORL A,R7 50 H JNC rel 51 H ACALL addr11 52 H ANL direct,A 53 H ANL direct,#data 54 H ANL A,#data 55 H ANL A,direct 56 H ANL A,@R0 57 H ANL A,@R1 58 H ANL A,R0 59 H ANL A,R1 5A H ANL A,R2 5B H ANL A,R3 5C H ANL A,R4 5D H ANL A,R5 5E H ANL A,R6 5F H ANL A,R7 C0 H PUSH direct C1 H AJMP addr11 C2 H CLR bit Opcode 60 H 61 H 62 H 63 H 64 H 65 H 66 H 67 H 68 H 69 H 6A H 6B H 6C H 6D H 6E H 6F H 70 H 71 H 72 H 73 H 74 H 75 H 76 H 77 H 78 H 79 H 7A H 7B H 7C H 7D H 7E H 7F H 80 H 81 H 82 H 83 H 84 H 85 H 86 H 87 H 88 H 89 H 8A H 8B H 8C H 8D H 8E H 8F H F0 H F1 H F2 H Mnemonic JZ rel AJMP addr11 XRL direct,A XRL direct,#data XRL A,#data XRL A,direct XRL A,@R0 XRL A,@R1 XRL A,R0 XRL A,R1 XRL A,R2 XRL A,R3 XRL A,R4 XRL A,R5 XRL A,R6 XRL A,R7 JNZ rel ACALL addr11 ORL C,direct JMP @A+DPTR MOV A,#data MOV direct,#data MOV @R0,#data MOV @R1,#data MOV R0.#data MOV R1.#data MOV R2.#data MOV R3.#data MOV R4.#data MOV R5.#data MOV R6.#data MOV R7.#data SJMP rel AJMP addr11 ANL C,bit MOVC A,@A+PC DIV AB MOV direct,direct MOV direct,@R0 MOV direct,@R1 MOV direct,R0 MOV direct,R1 MOV direct,R2 MOV direct,R3 MOV direct,R4 MOV direct,R5 MOV direct,R6 MOV direct,R7 MOVX @DPTR,A ACALL addr11 MOVX @R0,A
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 12 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Opcode 93 H 94 H 95 H 96 H 97 H 98 H 99 H 9A H 9B H 9C H 9D H 9E H 9F H A0 H A1 H A2 H A3 H A4 H A5 H A6 H A7 H A8 H A9 H AA H AB H AC H AD H AE H AF H B0 H B1 H B2 H B3 H B4 H B5 H B6 H B7 H B8 H B9 H BA H BB H BC H BD H BE H BF H Mnemonic MOVC A,@A+DPTR SUBB A,#data SUBB A,direct SUBB A,@R0 SUBB A,@R1 SUBB A,R0 SUBB A,R1 SUBB A,R2 SUBB A,R3 SUBB A,R4 SUBB A,R5 SUBB A,R6 SUBB A,R7 ORL C,bit AJMP addr11 MOV C,bit INC DPTR MUL AB MOV @R0,direct MOV @R1,direct MOV R0,direct MOV R1,direct MOV R2,direct MOV R3,direct MOV R4,direct MOV R5,direct MOV R6,direct MOV R7,direct ANL C,bit ACALL addr11 CPL bit CPL C CJNE A,#data,rel CJNE A,direct,rel CJNE @R0,#data,rel CJNE @R1,#data,rel CJNE R0,#data,rel CJNE R1,#data,rel CJNE R2,#data,rel CJNE R3,#data,rel CJNE R4,#data,rel CJNE R5,#data,rel CJNE R6,#data,rel CJNE R7,#data,rel Table 7 - Instruction Set Summary Opcode Mnemonic C3 H CLR C C4 H SWAP A C5 H XCH A,direct C6 H XCH A,@R0 C7 H XCH A,@R1 C8 H XCH A,R0 C9 H XCH A,R1 CA H XCH A,R2 CB H XCH A,R3 CC H XCH A,R4 CD H XCH A,R5 CE H XCH A,R6 CF H XCH A,R7 D0 H POP direct D1 H ACALL addr11 D2 H SETB bit D3 H SETB C D4 H DA A D5 H DJNZ direct,rel D6 H XCHD A,@R0 D7 H XCHD A,@R1 D8 H DJNZ R0,rel D9 H DJNZ R1,rel DA H DJNZ R2,rel DB H DJNZ R3,rel DC H DJNZ R4,rel DD H DJNZ R5,rel DE H DJNZ R6,rel DF H DJNZ R7,rel E0 H MOVX A,@DPTR E1 H AJMP addr11 E2 H MOVX A,@R0 E3 H MOVX A,@R1 E4 H CLR A E5 H MOV A,direct E6 H MOV A,@R0 E7 H MOV A,@R1 E8 H MOV A,R0 E9 H MOV A,R1 EA H MOV A,R2 EB H MOV A,R3 EC H MOV A,R4 ED H MOV A,R5 EE H MOV A,R6 EF H MOV A,R7 Opcode F3 H F4 H F5 H F6 H F7 H F8 H F9 H FA H FB H FC H FD H FE H FF H Mnemonic MOVX @R1,A CPL A MOV direct,A MOV @R0,A MOV @R1,A MOV R0,A MOV R1,A MOV R2,A MOV R3,A MOV R4,A MOV R5,A MOV R6,A MOV R7,A
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 13 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
80C152 Register Set Descriptions
The following are detailed descriptions for the IA80C152 register set. This register set is the same for all versions of the IA80C152. There is no difference between the IA80C152 register set and the register set for the original device. In addition to the registers listed below, there are four banks of eight general purpose registers (R0 through R7) which reside within internal RAM space. Selection of these register banks is controlled through the Program Status Word (PSW). The register descriptions are listed in alphanumeric order. The asterisk (*) indicates the register is bit addressable.
A* (0E0h) - Accumulator register used for various memory, arithmetic, and logic operations. ADR0,1,2,3 (095h, 0A5h, 0B5h, 0c5h) - Address match registers contain the values which determine which data will be accepted as valid. If using 8 bit addressing mode a match with any of the four registers will cause the data to be accepted. If using 16 bit addressing mode a match with the pairs ADR1 and ADR2 or ADR3 and ADR2 will cause the data to be accepted. A received address of all 1s will be accepted regardless of whether the address mode is 16 bit or 8 bit. B* (0F0h) - B register used for multiply and divide instructions. May also be used as a general purpose register. AMSK0,1 (0D5h, 0E5h) - Address Match Mask registers are used to set the corresponding bit in Address match registers to don' care. Setting the bit to a one in the AMSK register sets the corresponding bit in the ADR register to don' care. t t BAUD (094h) - Contains the value to be used by the baud rate determining equation. The value written to BAUD will actually be stored in a reload register. When the BAUD register contents are decremented to 00H the BAUD register will be reloaded from the reload register. Reading the BAUD register yields the current baud rate timer value. A read during a GSC operation may not give the current value since the value in BAUD could decrement after it is read and before the read value can be stored in its destination. BCRL0, BCRH0 (0E2h, 0E3h) - Byte count register high and low bytes for DMA channel 0. The two registers provide a 16-bit value representing for the number of DMA transfers via channel 0. Valid count range is from 0 to 65535. BCRL0, BCRH0 (0F2h, 0F3h) - Byte count register high and low bytes for DMA channel 1. The two registers provide a 16-bit value representing for the number of DMA transfers via channel 1. Valid count range is from 0 to 65535. BKOFF (0C4h) - An 8 bit count down timer with a clock period equal to one slot time. A user may read the register, but the register is clocked asynchronously to the CPU so invalid data can result. Writing to BKOFF will have no effect. DARL0, DARH0 (0C2h, 0C3h) - Destination address register high and low bytes for DMA channel 0. The two registers provide a 16-bit value representing the address of the destination for a DMA transfer via channel 0. Valid address range is from 0 to 65535. DARL0, DARH0 (0D2h, 0D3h) - Destination address register high and low bytes for DMA channel 1. The two registers provide a 16-bit value representing the address of the destination for a DMA transfer via channel 1. Valid address range is from 0 to 65535. DCON0,1 (092h, 093h) - DCON0 and DCON1 control DMA channel 0 or 1, respectively. Each bit in these 8-bit registers control the DMA transfer as described below. 7 DAS 6 IDA 5 SAS 4 ISA 3 DM 2 TM 1 DONE 0 GO
DAS - This bit in conjunction with IDA determine the destination address space.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 14 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
IDA - If IDA is set to 1 then the destination address is automatically incremented after the transfer of each byte. DAS 0 0 1 1 IDA 0 1 0 1 Destination External Ram External Ram SFR Internal RAM Auto-Increment NO YES NO YES
SAS - This bit in conjunction with ISA determine the source address space. ISA - If ISA is set to 1 then the source address is automatically incremented after the transfer of each byte. SAS 0 0 1 1 ISA 0 1 0 1 Source External Ram External Ram SFR Internal RAM Auto-Increment NO YES NO YES
DM - If this bit is set to a 1 then the DMA channel operates in demand mode. In this mode the DMA is initiated by either an external signal or by a serial port flag depending on the value of the TM bit. If the DM bit is set to a 0 then DMA is initiated by setting the GO bit. TM - If DM is 1 then TM selects if DMA is initiated by an external signal (TM=1) or by a serial port bit (TM=0). If DM is 0 then TM selects whether DMA transfers are in burst mode (TM=1) or in alternate cycles mode (TM=0). DM 0 0 1 1 TM 0 1 0 1 Mode Alternate Cycles Burst Serial Port Demand External Demand
DONE - This bit indicates that the DMA operation has completed. It also causes an interrupt. This bit is set to 1 when BCRn equals 0 and is set to 0 when the interrupt is vectored to. The user can also set and clear this bit. GO - If this bit is set to 1 it enables the DMA channel. DPL, DPH (082h, 083h) - DPTR, or the "data pointer" consists of the two 8-bit registers, DPL and DPH. The DPTR must be used for accesses to external memory requiring 16-bit addresses. GMOD (084h) - An 8-bit register that controls the GSC Modes as described below. 7 XTCLK 6 M1 5 M0 4 AL 3 CT 2 PL1 1 PL0 0 PR
PR - If set to a 1 the GSC is in SDLC mode. If set to a 0 the GSC is in CSMA/CD mode. PL0,1 - Preamble length: PL1 0 0 1 1 PL0 0 1 0 1 Preamble length in bits 0 8 32 64
The length noted in the table includes the two bit BOF in CSMA/CD mode but not the SDLC flag. Zero length preamble is not compatible with CSMA/CD mode. CT - This bit determines the CRC type used. If set to a 1 the 32 bit AUTODIN II-32 is used. If set to a 0 the 16 bit
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 15 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
CRC-CCITT is used. AL - This bit determines the address length used. If set to a 1 the 16 bit addressing is used. If set to a 0 the 8 bit addressing is used. M1,M0 - These bits contain the backoff mode select bits as defined in the following table. M1 0 0 1 1 M0 0 1 0 1 Mode Normal Raw Transmit Raw Receive Alternate Backoff
In Raw Receive mode the transmitter operates normally. The receiver operates normally except that all the bytes following the BOF are loaded into the receive FIFO including the CRC. In the Raw Transmit mode the receiver operates as normal and zero bit detection is performed. The transmit output is driven from the receiver input. Data transmitted is done so without a preamble, flag or zero bit insertion and without a CRC. In the Alternate Backoff mode the backoff is modified so it is delayed until the end of the IFS. Since the IFS time is generally longer than the slot time this should help to prevent collisions. XTCLK - This bit enables the use of an external transmit clock. A 1 enables the external clock (input on port 1, bit 3), a zero enables the internal baud rate generator. IE* (0A8h) - The Interrupt Enable register allows the software to select which interrupts are enabled per the table below. If a bit is 0, the interrupt is disabled. If a bit is 1, the interrupt is enabled. 7 EA 6 5 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
EA - Enable All interrupts. This bit globally enables or disables all interrupts regardless of the state of the individual bits. ES - Enable or disable serial port interrupt. ET1 - Enable or disable Timer 1 overflow interrupt. EX1 - Enable or disable External Interrupt 1. ET0 - Enable or disable Timer 0 overflow interrupt. EX0 - Enable or disable External Interrupt 0. IEN1* (0C8h) - The Interrupt Enable Number 1 register allows the software to select which interrupts are enabled per the table below. If a bit is 0, the interrupt is disabled. If a bit is 1, the interrupt is enabled. 7 6 5 EGSTE 4 EDMA1 3 EGSTV 2 EDMA0 1 EGSRE 0 EGSRV
EGSTE - Enable or disable GSC Transmit Error interrupt. EDMA1 - Enable or disable DMA channel 1 interrupt. EGSTV - Enable or disable GSC Transmit Valid interrupt. EDMA0 - Enable or disable DMA channel 0 interrupt.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 16 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
EGSRE - Enable or disable GSC Receive Error interrupt. EGSRV - Enable or disable GSC Receive Valid interrupt. IFS (0A4h) - The Interframe Spacing register determines the number of bit times between transmitted frames in both CSMA/CD and SDLC. Only even bit times can be used. The number written to this register is divided by two and loaded into the seven most significant bits. An interframe space is created by counting down this seven bit number twice. The value read from this register is the current count value in the upper seven bits and the first or second count down in the LSB. A 1 indicates the first count down and a 0 indicates the second count down. The value may not be valid since the register is clocked asynchronously to the CPU. IP* (0B8h) - The Interrupt Priority register allows the software to select which interrupts have a higher than normal priority. If a bit is 0, the interrupt has normal priority. If a bit is 1, the interrupt has a higher priority. When multiple bits are set to higher priority, interrupts are resolved in the same order as their normal priority setting. 7 6 5 4 PS 3 PT1 2 PX1 1 PT0 0 PX0
PS - Set normal or higher priority level for serial port interrupt. PT1 - Set normal or higher priority level for Timer 1 overflow interrupt. PX1 - Set normal or higher priority level for External Interrupt 1. PT0 - Set normal or higher priority level for Timer 0 overflow interrupt. PX0 - Set normal or higher priority level for External Interrupt 0. IPN1* (0F8h) - The Interrupt Enable Number 1 register allows the software to select which interrupts have a higher than normal priority. If a bit is 0, the interrupt has normal priority. If a bit is 1, the interrupt has a higher priority. When multiple bits are set to higher priority, interrupts are resolved in the same order as their normal priority setting. 7 6 5 PGSTE 4 PDMA1 3 PGSTV 2 PDMA0 1 PGSRE 0 PGSRV
PGSTE - Set normal or higher priority level for GSC Transmit Error interrupt. PDMA1 - Set normal or higher priority level for DMA channel 1 interrupt. PGSTV - Set normal or higher priority level for GSC Transmit Valid interrupt. PDMA0 - Set normal or higher priority level for DMA channel 0 interrupt. PGSRE - Set normal or higher priority level for GSC Receive Error interrupt. PGSRV - Set normal or higher priority level for GSC Receive Valid interrupt. MYSLOT (0F5h) - Register that controls the slot address for the devices as well as the type of Jam used and which backoff algorithm is used during a collision. 7 DCJ 6 DCR 5 SA5 4 SA4 3 SA3 2 SA2 1 SA1 0 SA0
SA5-0 - The six slot address bits determine not only the address but also the priority. Addresses 0 through 63 are available with 63 having the highest priority and 1 the lowest. An address of 0 will prevent a station from transmitting during the collision resolution period. DCR - The Deterministic Collision Resolution register determines which resolution algorithm to use. Setting this bit
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 17 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
to a 1 selects the alternate collision resolution algorithm. Also disabled by setting this bit is the retriggering of the IFS on the reappearance of the carrier. Alternate Backoff mode must be used with this feature. The user must initialize TCDCNT with the maximum number of slots that are appropriate for the system. To disable the PBRS this register must be set to all 1s. DCJ - A 1 selects DC type jam. A 0 selects AC type jam. P0*, P1*, P2*, P3*, P4*, P5, P6 (080h, 090h, 0A0h, 0C0h, 091h, 0A1h) - These registers are for I/O as defined in the table below. Most registers have a dual function. P5 and P6 are not bit addressable and are only available in the JB and JD versions of the IC. P0 P1 P2 P3 P4 P5 P6 Port Function Bit Address Function Bit Address Function Bit Address Function Bit Address Function Bit Address Function Bit Address Function Address Bit 7 087h 097h 0A7h RDn 0B7h 0C7h Bit 6 086h HLDA 096h 0A6h WRn 0B6h 0C6h Bit 4 Bit 3 Bit 2 Multiplexed Address/Data 085h 084h 083h 082h HLD RXCn TXCn DENn 095h 094h 093h 092h Address and User Defined 0A5h 0A4h 0A3h 0A2h T1 T0 INT1n INT0n 0B5h 0B4h 0B3h 0B2h User Defined 0C5h 0C4h 0C3h 0C2h User Defined 091h User Defined 0A1h Bit 5 Bit 1 081h GTXD 091h 0A1h TXD 0B1h 0C1h Bit 0 080h GRXD 090h 0A0h RXD 0B0h 0C0h
PCON (087h) - The POwer CONtrol register controls the power down and idle states of the 80C152 as well as various UART, GSC, and DMA functions as defined below. 7 SMOD 6 ARB 5 REQ 4 GAREN 3 XRCLK 2 GFIEN 1 PD 0 IDL
SMOD - Doubles the baud rate of the UART if the bit is set to 1. ARB - The DMA (both channels) is put into ARBiter mode if the bit is set to 1. REQ - The DMA (both channels) is put into REQuester mode if the bit is set to 1. GAREN - The GSC Auxiliary Receive Enable allows the GSC to receive back-to-back SDLC frames by setting the bit to 1. This bit has no effect in CSMA mode. XRCLK - Setting this bit enables the External Receive Clock to be used by the receiver portion of the GSC. GFIEN - The GSC Flag Idle Enable bit generates idle flags between transmitted SDLC frames when this bit is set to a 1. This bit has no effect in CSMA mode. PD - The Power Down bit puts the 80C152 into the power down power saving mode by setting this bit to a 1. IDL - The IDLe bit puts the 80C152 into the idle power saving mode by setting this bit to a 1. PRBS (0E4h) - This register contains the pseudo-random number to be used in the CSMA/CD backoff algorithm. The number is generated by using a feedback shift register clocked by the CPU phase clocks. Writing all 1s to this register will cause the register to freeze at all 1s. Writing any other value to it will cause it to start again. A read of this register will not always give the seed value due to the register being clocked by the CPUs phase clocks.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 18 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
PSW* (0D0h) - The Program Status Word register provides arithmetic and other microcontroller status as well as control for the selection of register banks 0 through 4. 7 CY 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 0 P
CY - Carry Flag set to 1 if an instruction execution results in a carry. AC - Auxiliary Carry Flag set to 1 if an instruction execution results in a carry. F0 - Flag 0 available for user defined general purpose. RS1, RS0 - Register bank Select 1 bit and Register bank Select 0 bit in combination define the current register bank to be used by the microprocessor. See table below. Register Bank 0 1 2 3 RS1 0 0 1 1 RS0 0 1 0 1 Register Bank Addresses 00h-07h 08h-0Fh 10h-17h 18h-1fh
OV - The OVerflow bit indicates an arithmetic overflow when set to a 1. P - Parity flag set or cleared by the hardware each instruction to indicate odd or even number of 1's in the accumulator. RFIFO (0F4h) - This is a 3 byte buffer which points to the oldest data in the buffer. The buffer is loaded with receive data every time the receiver receives a new byte of data. RSTAT* (0E8h) - This register provides status of the GSC receiver as defined below. 7 OR 6 RCABT 5 AE 4 CRCE 3 RDN 2 RFNE 1 GREN 0 HABEN
HABEN - The Hardware Based Acknowledge Enable when set to a 1 enables this feature. GREN - When this bit is set the receiver is enabled to accept incoming frames. RFIFO should be cleared before setting this bit by reading RFIFO until RFNE = 0. This should be done since setting GREN to a 1 clears RFIFO. It takes twelve clock cycles for the status of RFNE to be updated after a read of RFIFO. Setting GREN also clears RDN, CRCE, AE and RCABT. GREN is cleared by hardware at the end of a reception or if receive errors are encountered. The user is responsible for setting this bit to a 1. The user or the GSC can set this bit to a 0. In CSMA/CD mode the status of GREN has no effect on whether the receiver detects a collision since the receiver always monitors the receive pin. RFNE - This bit if set indicates that the receive FIFO is not empty. This flag is controlled by the GSC. If all the data is read from the FIFO the GSC will clear the bit. RDN - This bit is controlled by the GSC and if set indicates a successful receive operation has occurred. This bit will not be set if a CRC, alignment, abort, or FIFO overrun error occurred. CRCE - This bit is controlled by the GSC and if set indicates that a properly aligned frame was received without a mismatched CRC. AE - This bit is set by the GSC in CSMA/CD mode to indicate that the receiver shift register is not full and the CRC is bad when the EOF was detected. If the CRC is correct AE will not be set and a misalignment will be assumed to be caused by ` dribble bits'as the line went idle. In SDLC mode AE is set if a non-byte aligned flag is received. CRCE may also be set. RCABT - This bit is set by the GSC when a collision is detected after data has been loaded into the receive FIFO in
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 19 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
CSMA/CD mode. In SDLC mode this bit indicates that 7 consecutive 1s were detected before an end flag but after data was loaded into the receive FIFO. AE may also be set. OR - This bit is set by the GSC to indicate that the receive FIFO was full and then new data was shifted into it. AE and /or CRCE may also be set. This flag is cleared by the user. SARL0, SARH0 (0A2h, 0A3h) - Source address register high and low bytes for DMA channel 0. The two registers provide a 16-bit value representing the address of the source for a DMA transfer via channel 0. Valid address range is from 0 to 65535. SARL1, SARH1 (0B2h, 0B3h) - Source address register high and low bytes for DMA channel 1. The two registers provide a 16-bit value representing the address of the source for a DMA transfer via channel 1. Valid address range is from 0 to 65535. SBUF (099h) - Writes to this register load the transmit register, and reads access the receive register. SCON* (098h) - This register controls the set up of the UART as defined by the table below. 7 SM0 Mode 0 1 2 3 6 SM1 SM0 0 0 1 1 5 SM2 SM1 0 1 0 1 4 REN 3 TB8 Description Shift Register 8-bit UART 9-bit UART 9-bit UART 2 RB8 1 TI 0 RI
SM0, SM - The combination of these 2 bits controls the mode and type of baud rate. Baud Rate (Osc. Freq.)/12 Variable (Osc. Freq.)/64 or (Osc. Freq.)/32 Variable
SM2 - When this bit is set and the UART mode is 1, RI will not be activated unless a valid stop bit is received. When this bit is set and the UART mode is 2 or 3, RI will not be activated if the 9th bit is 0. REN - Setting this bit enables the UART to receive. Clearing this bit disables UART reception. TB8 - In modes 2 and 3, the value of this bit is transmitted during the 9th bit time. This bit is set or cleared by software. RB8 - In modes 2 and 3, this bit is the value of the 9th bit that was received by the UART. In mode 1, this bit is the value of the stop bit received by the UART. TI - Transmit Interrupt flag set by hardware upon at the end of the 8th bit in mode 0 or at the beginning of the stop bit in modes 1, 2, or 3. This bit must be cleared by software to clear the interrupt. RI - Receive Interrupt flag set by hardware at the end of the 8th bit in mode 0 or halfway through the stop bit in modes 1, 2, or 3. This bit must be cleared by software to clear the interrupt. SLOTTM (0B4h) - Determines the length of the slot time in CSMA/CD mode. A slot time equals SLOTTM * (1 / baud rate). Reads from this location are unreliable since this register is clocked asynchronously to the CPU. Loading a value of 0 results in a slot time of 256 bit times. SP (081h) - This register is the stack pointer. Its value points to the memory location that is the beginning of the stack. TCDCNT (0D4h) - If probabilistic CSMA/CD is used this register contains the number of collisions. The user must clear this register before transmitting a new frame so the GSC can distinguish between a new frame and the retransmit of a frame. In deterministic backoff mode TCDCNT is used to hold the maximum number of slots. TCON* (088h) - This register controls the operation of the Timers 0 and 1 and External Interrupts 0 and 1 as defined by the table below.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 20 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 TF1 - Timer overFlow 1 interrupt flag set by hardware when timer 1 overflows. Hardware clears this flag when the processor vectors to the interrupt service routine. TR1 - Timer Run 1 flag set by software to turn on timer 1 and cleared by software to turn off timer 1. TF0 - Timer overFlow 0 interrupt flag set by hardware when timer 0 overflows. Hardware clears this flag when the processor vectors to the interrupt service routine. TR0 - Timer Run 0 flag set by software to turn on timer 0 and cleared by software to turn off timer 0. IE1 - Interrupt External 1 flag set by hardware when an edge is detected on External Interrupt 1. Hardware clears this flag when the processor vectors to the interrupt service routine. IT1 - Interrupt Trigger 1 flag is set by software to specify a falling edge triggered interrupt for External Interrupt 1. The flag is cleared by software to specify a low level triggered interrupt for External Interrupt 1. IE0 - Interrupt External 0 flag set by hardware when an edge is detected on External Interrupt 0. Hardware clears this flag when the processor vectors to the interrupt service routine. IT0 - Interrupt Trigger 0 flag is set by software to specify a falling edge triggered interrupt for External Interrupt 0. The flag is cleared by software to specify a low level triggered interrupt for External Interrupt 0. TFIFO (085h) - This is the 3 byte buffer used for storing transmit data. If TEN is set to a 1 transmission begins as soon as data is written to TFIFO. TH0, TL0 (08Ch, 08Ah) - These registers provide the high byte (TH0) and low byte (TL0) values for Timer 0. These registers may be used together or separately depending on Timer 0 mode bits. TH1, TL1 (08Dh, 08Bh) - These registers provide the high byte (TH0) and low byte (TL0) values for Timer 0. These registers may be used together or separately depending on Timer 0 mode bits. TMOD (089h) - This register controls the set up and modes of Timers 0 and 1 as defined by the table below. 7 GATE 6 Timer 1 C/Tn M1 M0 GATE C/Tn 5 4 3 2 Timer 0 M1 M0 1 0
GATE - When this bit is set, Timers/Counters may be turned on or off by the corresponding External Interrupt, if the appropriate TR bit is set. When this bit is cleared, Timers/Counters may only be turned on or off by the appropriate TR bit. C/Tn - Counter/Timer flag. Set by software for Counter operation, cleared by software for Timer operation. M1, M0 - Set the mode of the Timers/Counters as defined by the table below. Mode 0 1 2 3 M1 0 0 1 1 M0 0 1 0 1 Description 13-bit Timer 16-bit Timer/Counter 8-bit Auto Reload Timer/Counter One 8-bit Timer/Counter (TL0) controlled by Timer 0 control bits. One 8-bit Timer/Counter (TH0) controlled by Timer 1 control bits.
TSTAT* (0D8h) - This register provides status of the GSC transmitter as defined below.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 21 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
7 LNI 6 NOACK 5 UR 4 TCDT 3 TDN 2 TFNF 1 TEN 0 DMA
DMA - If this bit is set it indicates that the DMA channels are used to service the RFIFO and TFIFO and that GSC interrupts occur on TDN and RDN. If set it also enables UR to become set. If this bit is cleared it indicates that the GSC is operating in normal mode and interrupts occur on TFNF and RFNE. TEN - When TEN is set it will cause TDN, UR, TCDT and NOACK to be reset and the TFIFO to be cleared. The transmitter will clear TEN after a successful transmission, a collision during data, CRC or end flag. The user sets the bit and the user of the GSC can clear the bit. If the bit is cleared during a transmission the transmit pin goes to a high level. This is the method used to send an abort character in SDLC. DEN is also forced to a high level. An end of transmission occurs whenever the TFIFO is emptied. TFNF - If this bit is a 1 TFIFO is not full and new data may be written to it. TDN - The GSC sets this bit to indicate that a frame transmission completed successfully. If HABEN is set, TDN will not be set until the end of the IFS so that the acknowledge can be checked. TDN will not be set if an acknowledge is expected but not received. An acknowledge will not be expected after a broadcast or a multi-cast packet. TCDT - The GSC sets this bit to indicate that the transmission stopped due to a collision. The bit is set by a collision occurring during the data, the CRC or if there are more than 8 collisions. UR - The GSC sets this bit to indicate that in DMA mode the last bit was shifted out of the transmit register and that the DMA byte count did not equal 0. When this occurs the transmitter stops without sending the CRC and the end flag. NOACK - The GSC sets this bit to indicate that an acknowledge was not received for the previous frame. This bit will be set only if HABEN is set and no acknowledge is received before the end of the IFS. NOACK will not be set following a broadcast or a multi-cast packet. LNI - The GSC sets this bit to indicate that the receive line is idle. In CSMA/CD mode LNI is set if GRXD remains high for ~ 1.6 bit times. LNI is cleared after a transition on GRXD. In SDLC node LNI is set if 15 consecutive ones are received.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 22 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Absolute Maximum Ratings
AC/DC Parameters
Ambient temperature under bias....................................-40C to +85C (2) Operating temperature... ... ... ... ... ... ... ... ... ... ..... -40C to +85C Storage temperature..................................... ...................-65C to +150C Voltage on any pin to VSS.............................................-0.3 to (VDD +0.3) Power dissipation.................................................... ........391.1 mW (95C, 16MHz, 15% Toggle)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Operating the device beyond the conditions indicated in the "recommended operating conditions" section is not recommended. Operation at the "absolute maximum ratings" may adversely affect device reliability.
Notes: Design, Static and Dynamic Timing Characterization in Progress.
Table 8: DC Characteristics
Symbol VIL VIL1 VIH VIH1 VOL VOL1 VOH Parameter Input Low Voltage (All Except EAn, EBEN) Input Low Voltage (EAn, EBEN) Input High Voltage ( Except XTAL1, RSTn) Input High Voltage ( XTAL1 RSTn) Output Low Voltage (Ports 1, 2, 3, 4, 5, 6) Output Low Voltage (Ports 0, ALE.PSENn, EPSENn) Output High Voltage (Ports 1, 2, 3, 4, 5, 6, COMM9 ALE, PSENn, EPSENn) Output High Voltage (Port 0 in External Bus Mode) Logical 0 Input Current (Ports 1, 2, 3, 4, 5, 6) Logical 1 to 0 Transition Current (Ports 1, 2, 3, 4, 5, 6) Input Leakage ( Port 0, EAn) Reset Pull-up Resistor Logical 1 Input Current (EBEN) Power Supply Current: Active (16.5 MHz) Idle(16.5 MHz) Power Down Mode Min Typ Max Unit V V V V V V V V V V A Test Conditions
VOH1
IIL ITL ILI RRST IIH IDD
A A k A mA mA A
100
(1)
Notes:
(1) Static Idd current is exclusive of input/output drive requirements and is measured with the clocks stopped and all inputs tied to Vdd or Vss, configured to draw minimum current. (2) The input and output parametric values in section VII-B, parts 1, 2, and 3, are directly related to ambient temperature and DC supply voltage. A temperature or supply voltage range other than those specified in the Operating Conditions above will affect these values and part performance is not guaranteed by innovASIC.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 23 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
A. C. Characteristics
Table 9:External Program and Data Memory Characteristics
Symbol 1/TCLCL Parameter Oscillator Frequency 80C152JA/JC 83C152JA/JC 83C152JB/JD 80C152JA/JC-1 83C152JA/JC-1 80C152JB/JD-1 ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSENn Low PSENn Pulse Width PSENn Low to Valid Instruction In Input Instruction Hold After PSENn Input Instruction Float After PSENn Address to Valid Instruction In PSENn Low to Address Float RDn Pulse Width WRn Pulse Width RDn Low to Valid Data In Data Hold After RDn Data Float After RDn ALE Low to Valid Data In Address to Valid Data In ALE Low to RDn or WRn Low Address to RDn or WRn Low Data Valid to WRn Transition Data Hold After WRn RDn Low to Address Float RDn or WRn High to ALE High 16.5 MHz Min Max Variable Oscillator Unit Min 3.5 Max MHZ 12 MHZ 3.5 16.5 ns ns ns ns ns ns ns 0 0 ns ns ns ns ns ns ns 0 0 ns ns ns ns ns ns ns ns ns ns
TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TWHQX TRLAZ TWHLH
0
0
Input leakage is 1A
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 24 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Figure 6: External Program Memory Read Cycle
TLHLL ALE TLLPL TLLIV TPLIV TAVLL PSENn/EPSENn TPLPH
TPLAZ TLLAX PORT0/PORT5 A0-A7 INSTR IN
TPXIZ TPXIX A0-A7
TAVIV PORT2/PORT6 A8-A15 A8-A15
Figure 7: External Data Memory Read Cycle
ALE TLLDV PSENn TLLWL RDn TLLAX TAVLL PORT0
A0-A7 FROM R OR DPL
TWHLH
TRLRH
TRLAZ TRLDV DATA IN
TRHDZ TRHDX
A0-A7 FROM PCL
INSTR. IN
TAVWL TAVDV PORT2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 25 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Figure 8: External Data Memory Write Cycle
ALE
PSENn TLLWL WRn TWLWH TWHLH
TLLAX TAVLL PORT0
A0-A7 FROM R OR DPL
TQVWX DATA OUT
TWHQX
A0-A7 FROM PCL
INSTR. IN
TAVWL PORT2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
Table 10: External Clock Drive
Symbol 1/TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency High Time Low Time Rise Time Fall Time Min 3.5 20 20 Max 16.5 Units MHz ns ns ns ns
20 20
Figure 9: External Clock Drive Waveform
Vcc - 0.5 0.7 Vcc
0.45V
0.2 Vcc - 0.1 TCHCL TCLCX TCLCL
TCHCX TCLCH
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 26 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Table 11: Local Serial Channel Timing - Shift Register Mode
Symbol TXLXL TQVXH TXHQX TXHDX TXHDV Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid Min 16.5 MHz Max Variable Oscillator Min 12TCLCL Units Max ns ns ns ns ns
Figure 10: Shift Register Mode Timing Waveforms
INSTRUCTION | ALE 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
TXLXL CLOCK
TQVXH TXHQX OUTPUT_DATA |_________| ^ |
WRITE TO SBUF
0
1
2
3
4
5
6
7 ^ | SET T1
TXHDX TXHDV
INPUT_DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
|____________| ^ |
CLEAR R1
^ | SET R1
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 27 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Table 12: Global Serial Port Timings - Internal Baud Rate Generator
Symbol HBTJR Parameter Allowable jitter on the Receiver for 1/2 bit time (Manchester encoding only) Allowable jitter on the Receiver for one full bit time (NRZI and Manchester) Jitter of data from Transmitter for 1/2 bit time (Manchester encoding only) Jitter of data from Transmitter for one full bit time (NRZI and Manchester) Data rise time for Receiver Data fall time for Receiver 16.5 MHz (BAUD = 0) Min Max 0.0375 s 0.10 s 10 10 ns 10 10 ns 20.00 20.00 20.00 20.00 ns ns Variable Oscillator Min Max Unit
FBTJR
HBTJT
FBTJT
DRTR DFTR
Figure 11: GSC Receiver Timings (Internal Baud Rate Generator)
HBTJR HBTJR MANCHESTER FBTJR GRxD FBTJR
BT FBTJR NRZI
FBTJR
GRxD
Figure 12: GSC Transmit Timings (Internal Baud Rate Generator)
HBTJT HBTJT MANCHESTER FBTJT GTxD FBTJT
BT FBTJT FBTJT NRZI GTxD
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 28 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Table 13: Global Serical Port Timings - External Clock
Symbol 1/ECBT ECH ECL ECRT ECFT ECDVT Parameter GSC Frequency with an External Clock External Clock High External Clock Low External Clock Rise Time External Clock Fall Time External Clock to Data Valid Out - Transmit (To External Clock Negative Edge) External Clock to Data Hold - Transmit (To External Clock Negative Edge) External Clock to Data Set-up - Receiver (To External Clock Positive Edge) External Clock to Data Hold - Receiver (To External Clock Positive Edge) 16.5 MHz Min Max 2.4 Variable Oscillator Min Max 0.009 Unit MHz ns ns ns ns
ns
ECDHT
ns
ECDSR
ns
ECDHR
ns
Figure 13: GSC Timings (External Clock)
ECBT ECL EXTERNAL_CLOCK ECH
ECDHT TRANSMIT_DATA
ECBT EXTERNAL_CLOCK
ECDVT
ECDHR ECDSR RECEIVE_DATA
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 29 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
PLCC Packaging Dimensions (Theta J = TBD)
1.22/1.07 2 PLCS
D
PIN 1 IDENTIFIER & ZONE
D1
E3
D3 TOP VIEW
E1
E
BOTTOM VIEW
.81 / .66
LEAD COUNT
Symbol 68 (in Millimeters) MIN 4.20 2.29 24.13 22.61 MAX 5.08 3.30 24.33 23.62
SEATING PLANE A
A A1
A1
D1 D2
e .51 MIN. .53 / .33 R 1.14 / .64
.10
D3 E1 E2 E3
D2 / E2 SIDE VIEW
20.32 BSC 24.13 22.61 24.33 23.62
20.32 BSC 1.27 BSC 25.02 25.02 25.27 25.27
e D E Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 30 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
PDIP Packaging Dimensions (Theta J = TBD)
TOP
E1
E
LEAD 1 IDENTIFIER
eA eB
1 LEAD COUNT DIRECTION
C
SIDE VIEW (WIDTH)
Lead Count
Symbol 48 (in Inches) MIN .015 .015 .040 .008 2.455 .580 .520 .100 TYP .580 .100 MIN .686 MAX .200 .020 .060 .012 2.460 .610 .560
D A
A A1 B B1
A1
C D
L B B1 e
E E1 e eA eB L B2 S
SIDE VIEW (LENGTH)
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 31 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Packaging Options
The IA80C152 is available in four versions, two package styles, and two environmental classes as shown in the table below. Package Type 48 Lead Plastic DIP, 600 mil wide 68 Lead Plastic Leaded Chip Carrier Version JA/JC JA/JC JB/JD Environment Industrial Commercial Industrial Commercial Industrial Commercial Order Number IA80C152JA/JC-PDW48I IA80C152JA/JC-PDW48C IA80C152JA/JC-PLC68I IA80C152JA/JC-PLC68C IA80C152JB/JD-PLC68I IA80C152JB/JD-PLC68C
The following diagram depicts the innovASIC Product Identification Number. IAXXXXX-PPPPNNNT/SP
Special Processing: S = Space Q = MIL-STD-883 Temperature: C = Commercial I = Industrial M = Military Number of Leads Package Type: Per Package Designator Table IC Base Number innovASIC Designator
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM
Page 32 of 32
IA80C152 Preliminary Data Sheet UNIVERSAL COMMUNICATIONS CONTROLLER
Package Designator Table Package Type
Ceramic side brazed Dual In-line Cerdip with window Ceramic leaded chip carrier Cerdip without window Ceramic leadless chip carrier PLCC Plastic DIP standard (300 mil) Plastic DIP standard (600 mil) Plastic metric quad flat pack Plastic thin quad flat pack Skinny Cerdip Small outline plastic gull-wing(150 mil body) Small outline medium plastic gull-wing (207 mil body) Small outline narrow plastic gull wing (150 mil body) Small outline wide plastic gull wing (300 mil body) Skinny Plastic Dip Shrink small outline plastic (5.3mm .208 body) Thin shrink small outline plastic Small outline large plastic gull wing (330 mil body) Thin small outline plastic gull-wing (8 x 20mm) [TSOP] PGA BGA
innovASIC Designator
CDB CDW CLC CD CLL PLC PD PDW PQF PTQ CDS PSO PSM PSN PSW PDS PS PTS PSL PST CPGA CBGA
Contact innovASIC for other package and processing options.
Copyright (c) 2000 innovASIC [_________The End of ObsolescenceTM

▲Up To Search▲

Price & Availability of IA80C152JD

	To Download IA80C152JD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .